Clock signals are used to coordinate actions of electrical circuits in an electrical circuit device. However, the duty cycle of these clock signals can be subject to distortion. A duty cycle of a clock signal is a ratio of the pulse time of the clock signal to its cycle period. A duty cycle of a clock signal can become distorted due to a variety of sources, including amplifiers that make up a clock tree, large propagation distances between amplifier stages of the clock tree, and/or parasitic conductor capacitance. Distortion of the duty cycle skews timing margins defined by the clock signal in electrical circuit devices. As a result, an electrical circuit using the distorted clock signal can have smaller timing windows in which to transfer and/or process data, which could lead to reduced pulse widths, data errors, and unreliable circuit performance. As input/output speeds increase (e.g., as the cycles of a clock signal are reduced), it also becomes increasingly more challenging to reduce duty cycle distortion, meaning that the consequences of duty cycle distortion at high input/output speeds are even more apparent. In addition, electrical circuits at different locations (e.g., on different electrical circuit dies) can experience varying degrees of duty cycle distortion of a clock signal due to differing sources of distortion located along the corresponding clock branches of a clock tree that define the clock signal pathways.
One or more duty cycle detectors (DCD) can be used in one or more locations of the electrical circuit device to detect distortions in the duty cycle of the clock signals. However, the DCD circuit can have an offset error (also referred to herein as “DCD offset”) due to offsets in components in the DCD circuit such as the reference clock path, the charge-discharge circuits, amplifier circuit, and comparator circuit. Thus, the output of the duty cycle detector can be based on both the DCD offset and the distortions in the duty cycle of the clock signals. When the DCD circuit has an offset error, it can be difficult to correct for the distortions in the duty cycle of the clock signal. For example, if the duty cycle distortions require a +3 adjustment correction and the DCD circuit has an offset error of +2, the adjustment to the duty cycle of the clock signal could end up being +5 instead of +3. In conventional circuits, a DCD circuit calibration could be performed to determine a trim value, known as a time output high (tOH) trim, to cancel the DCD offset. However, in some applications it may be difficult to directly sense the duty cycle of the clock signal at its source to perform the DCD circuit calibration.